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http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311194 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#StockK06 2007-07-19 Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs. 1-2 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311358 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#VeredasP06 2007-07-19 Can Graphics Processing Units be Used to Improve Video Processing Systems? 1-2 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311356 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#Cope06 2007-07-19 Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311264 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#DanneMP06 2007-07-19 A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311294 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#BieserBHSM06 2007-07-19 Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. 1-8 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311273 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#SinghalB06 2007-07-19 An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311218 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#YoshimiOINKFHSIKA06 2007-07-19 TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311233 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#SaldanaC06 2007-07-19 FPGA Vendor Agnostic True Random Number Generator. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311206 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#SchellekensPV06 2007-07-19 System Level Architecture Exploration for Reconfigurable Systems On Chip. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311195 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#MasselosTQVCRP06 2007-07-19 Power Optimization Techniques for SRAM-Based FPGAs. 1-2 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311362 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#MondalM06 2007-07-19 Detection Module in a Complementary Set of Sequences-Based Pulse Compression System. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311197 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#AlvarezHUGJT06 2007-07-19 Execution Objects for Dynamically Reconfigurable FPGA Systems. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311331 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#OliverM06 2007-07-19 Real-Time Video Pixel Matching. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311259 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#NoteSV06 2007-07-19 Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311327 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#OsanaYFHSIKA06 2007-07-19 Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311232 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#NikolovSD06 2007-07-19 A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311328 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#SaundersF06 2007-07-19 Defect-Tolerant FPGA Architecture Exploration. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311253 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#MaideeB06 2007-07-19 A Reconfigurable Viterbi Decoder for a Communication Platform. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311248 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#AhmedA06 2007-07-19 Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311251 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#CampregherCCV06 2007-07-19 A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311227 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#ShannonFPPSC06 2007-07-19 FPGA Architecture Design Methodology. 1 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311187 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#Hutton06 2007-07-19 Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311272 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#KassapakiMS06 2007-07-19 Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs. 1-2 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311359 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#BroxS06 2007-07-19 Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311287 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#OlivaresBHVZ06 2007-07-19 Minimizing Communication Cost for Reconfigurable Slot Modules. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311263 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#FeketeVMT06 2007-07-19 FPGA-Based Boundary-Scan Bist. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311281 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#OlozabalCV06 2007-07-19 Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311255 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#ZienerAT06 2007-07-19 A Flexible Implementation of a Temporal Filter with Motion Compensation. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311275 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#Perschke06 2007-07-19 On Feasibility of FPGA Bitstream Compression During Placement and Routing. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311306 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#StepienV06 2007-07-19 Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311260 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#BeauchampHUH06 2007-07-19 High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311341 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#Arce-NazarioJR06 2007-07-19 FPGA Implementation of High-Performance PHM / DPHM Schedulers. 1-4 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311326 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#SotoLR06 2007-07-19 Fast Emulation of Permanent Faults in VLSI Systems. 1-6 2006 FPL http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311221 http://www.informatik.uni-trier.de/~ley/db/conf/fpl/fpl2006.html#AndresRGG06 2007-07-19